(1) Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit including P-channel MOS (Metal Oxide Semiconductor) transistors having different threshold voltages.
(2) Description of the Prior Art
Recently, there has been considerable activity in the development of methods of reducing the feature size of an LSI pattern. Normally, the breakdown voltages of elements of the LSI circuit decrease as the feature size diminishes. From this point of view, use of a power supply voltage lower than a normal (external) power supply voltage has been proposed. Such a power supply voltage is called a dropped power supply voltage.
FIG.1 is a circuit diagram of a conventional semiconductor integrated circuit in which a normal power supply voltage V.sub.CC and a dropped power supply voltage V.sub.RC are used. The circuit shown in FIG.1 is composed of CMOS inverters 10 and 11, which are cascaded. The CMOS inverter 10 is, for example, an input circuit, and CMOS inverter 11 is, for example, a first stage of an internal circuit. The CMOS inverter 10 is composed of a P-channel MOS (PMOS) transistor 13 and an N-channel MOS (NMOS) transistor 14. The CMOS inverter 11 is composed of a PMOS transistor 15 and an NMOS transistor 16.
The normal power supply voltage V.sub.CC, which is generated by an external power source and equal to, for example, 5 V, is applied to the source of the PMOS transistor 13. The source of the NMOS transistor 14 is grounded (zero volt; GND). Hereinafter, the CMOS inverter 10 is referred to as a V.sub.CC system gate circuit 10. The dropped power supply voltage V.sub.RC, which is generated by an internal power supply circuit on the chip and equal to, for example, 4 V, is applied to the source of the PMOS transistor 15. The source of the NMOS transistor 16 is grounded. Hereinafter, the CMOS inverter 11 is referred to as a V.sub.RC system gate circuit 11.
An input signal, which is input to the potential V.sub.CC system gate circuit 10, has a high logic level (a binary numeral) approximately equal to the potential V.sub.CC (5 V) and a low logic level (a binary numeral) approximately equal to the ground potential GND (OV). When the input signal has the high logic level, the NMOS transistor 14 is ON and thus the V.sub.CC system gate circuit 10 outputs the low logic level to the V.sub.RC system gate circuit 11. A potential at which the PMOS transistor 13 turns ON from OFF is equal to a potential obtained by adding a threshold voltage V.sub.TH13 of the PMOS transistor 15 approximately equal to -0.6 V to the potential V.sub.CC.
The input signal of the V.sub.RC system gate circuit 11 (which corresponds to the output signal of the V.sub.CC system gate circuit) has a high logic level approximately equal to the potential V.sub.CC and a low logic level approximately equal to the ground potential GND. When the input signal of the V.sub.RC system gate circuit 11 has the high logic level, the NMOS transistor 16 is ON, and thus the V.sub.RC system gate circuit 11 generates the low logic level approximately equal to the ground potential GND. When the input signal of the V.sub.RC system gate circuit 11 has the low logic level, the PMOS transistor 15 is ON, and thus the V.sub.RC system gate circuit 11 generates the high logic level approximately equal to the potential V.sub.RC. A potential at which the PMOS transistor 15 turns ON from OFF is equal to a potential obtained by adding a threshold voltage V.sub.TH15 of the PMOS transistor 15 to the dropped potential V.sub.CC, and is approximately equal to -0.6 V.
In the above-mentioned way, the breakdown voltage of the V.sub.RC gate circuit 11 substantially increase by using the dropped power supply voltage V.sub.RC. Since the V.sub.CC system gate circuit 10 functions as the input buffer circuit, it is required to have a high driving ability. From this point of view, the normal power supply voltage V.sub.CC is applied to the V.sub.CC system gate circuit 10. The PMOS transistors 13 and 15 are produced by the same process.
However, the circuit shown in FIG. 1 has the following disadvantage arising from the fact that the threshold voltage V.sub.TH15 of the PMOS transistor 15 of the V.sub.RC system gate circuit 11 is the same as the threshold voltage V.sub.TH13 of the PMOS transistor 13 of the V.sub.CC system gate circuit 10. As shown in FIG. 2A, when the PMOS transistor 13 turns ON when the input signal decreases and becomes equal to 4.4 V. In this case, the PMOS transistor 13 has a threshold voltage of -0.6 V. It takes time t1 the PMOS transistor 13 to turn ON. Meanwhile, as shown in FIG.2B, the PMOS transistor 15 turns ON when the output signal of the V.sub.CC system gate circuit 10 decreases and becomes equal to 3.4 V (=+4 V+(-0.6 V)). Thus, it takes a time t2 longer than time t1 for the PMOS transistor 15 to turn ON. That is, the switching speed of the V.sub.RC system gate circuit 11 is smaller than that of the V.sub.CC system gate circuit 10.
As described above, the threshold voltage of the PMOS transistor corresponds to a gate potential with respect to the source potential. Thus, when the PMOS transistor 15 is produced under the same condition as the PMOS transistor 13, the threshold voltage V.sub.TH15 corresponds to a potential lower than the source potential by 0.6 V.
The above problem will take place in a circuit shown in FIG.3. Two V.sub.RC system circuits 17 and 18 are mutually connected via a PMOS transistor 19, which is driven by a V.sub.CC system gate circuit (CMOS inverter) 20. Since the PMOS transistor 19 has a long switching time, as described above with reference to FIG.2B, a delay in the signal transmission between the V.sub.RC system circuits 17 and 18 occurs.